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AR# 8807

2.1i COREGEN: Map WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output on Single Port Block Memory.

Description

Keywords: unconnected, core generator, block memory, virtex, ROM, RAM

Urgency: standard

General Description:

You may see MAP warnings similar to the following about the the higher order output bits of a
CORE Generator Single Port Block Memory being unconnected with Single Port Block
memories wider than 16 bits:

WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB4 of comp
u1/BU0 is not connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB5 of comp
u1/BU0 is not connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB6 of comp
u1/BU0 is not connected.

Solution

These warnings are normal when you generate a Single Port Block ROM which is wider
than 16 bits. The reason they may be seen is because the CORE Generator implements
such wide data word Single Port memory functions in a novel way that results in significant
savings in LUT resources. The methodology used is described on p. 9 of XAPP130:

http://www.xilinx.com/xapp/xapp130.pdf

Basically it involves interleaving the memory space, setting the LSB of the address bus
of Port A to 1 (VCC ), and the LSB of the address bus of Port B to 0 (GND).

In conjunction with this, the output of the wide memory is generated by concatenating
the bits from the two dual port output ports together. Usually all 16 bits from one
of the ports are used first, and the remaining bits are implemented using the LSBs of
the second output port. This may result in some MSBs on the second output port
being unconnected.
AR# 8807
Date Created 03/13/2000
Last Updated 09/05/2001
Status Archive
Type General Article