AR# 8816


FPGA Express - "ERROR:OldMap:56 - The LOC constraint '<pin_location>' (a IOB location) is not valid for symbol '<symbol_name>'"


General Description:

In any given design, resource requirements and limitations may require that certain clock or reset signals not be mapped onto global buffers. Similarly, a previously-laid out PCB may dictate the pins to which certain signals may be mapped.

By default, FPGA Express will infer a global buffer for high-fanout clock signals and will utilize dedicated clock pins (CLKIOB or GCLKIOB) when they are available. In the case where a signal is mapped (by Express) to a dedicated clock pin and subsequently locked to a regular IOB location by the user, the following error(s) will be reported during the MAP phase of implementation:

Virtex devices:


"ERROR:xvkmm:3 - Illegal LOC on symbol "reset.PAD" (pad signal=reset) or BUFGP symbol "C41" (output signal=N13_BUFGPed), IPAD-IBUFG should only be LOCed to GCLKIOB site."


"ERROR:MapLib:93 - Illegal LOC on symbol "clk4" (pad signal=clk4) or BUFGP symbol "C48" (output signal=clk4_BUFGPed), IPAD-IBUFG should only be LOCed to GCLKIOB site."

Non-Virtex devices:


"ERROR:OldMap:56 - The LOC constraint "P##" (a IOB location) is not valid for symbol "reset.PAD" (pad signal = reset), which is being mapped to the following site types: CLKIOB"


If you have Foundation Standard Express 2.1i software, you have the ability to enter certain design constraints through the FPGA Express GUI. If you have Base Express software, the constraints must be entered through the FPGA Express command shell. (For instructions on the latter, please see Resolution 2.)

To determine what software package you are using, open your license file and look for one of these codes:

FND-BSX-*** ... Base Express

FND-EXP-*** ... Standard Express

You must edit constraints for your synthesized design through FPGA Express in stand-alone mode. Open this through Start -> Programs -> Foundation Series -> Accessories -> FPGA Express. The .exp file that represents your existing FPGA Express project can be found in myproj/myproj/myproj.exp (where "myproj" is the name of your Foundation project).

Within FPGA Express, right-click on your synthesized design in the "Chips" window, and select "Edit Constraints". Then, select the "Ports" tab. In the column titled "Global Buffer", select "Don't Use" for the signal that you do not want mapped to a global buffer.

1. Open the FPGA Express GUI.

2. Open the project.

3. Highlight the "optimized" chip.

4. Select the "Script" pull-down menu.

5. Select "Export FPGA Script ..." and note the location to which you exported.

6. In NotePad, open the script from the location to which you exported.

7. In the script, type the following command into in the line after "current_chip <chip_name>," (see the example below):

set_pad_buffer "DONT USE" /<chip_name>/<clock_port>

8. Save the file by putting quotation marks around the file name to preserve its extension:

- The file should be saved as: "<design_name>.fes".

- Select "Yes" twice to save.

9. Open the FPGA Express Shell to source the script:

Start -> Programs -> Xilinx -> Accessories -> FPGA Express Shell

10. Navigate to the location of the script:


11. Source the FES file that you exported:

source filename.fes

12. You may now take this EDIF netlist and run an EDIF flow with Xilinx implementation tools.

Example script:

open_project <path_to_project>\<project>.exp

analyze_file -progress

create_chip -progress -name <chip_name> -target SPARTAN2 -device 2S150FG456 -speed -6 -frequency 200 -preserve <top_level>

current_chip <chip_name>

optimize_chip -name <chip_name>-Optimized -progress




The resulting script will be very basic, as FPGA Express does not export any constraints that you have created. Any constraints entered through the GUI must be re-entered in the script.

After the "create_chip" action has been performed, enter the following commands:

current_chip <chip_name>

set_pad_buffer "DONT USE" /<chip_name>/<clock_port>

You may now proceed with the rest of the script.

If you would like a signal to utilize the global routing resources, but not via the dedicated clock pin (perhaps because of a previously laid-out PCB), you can do so by instantiating an IBUF -> BUFG pair. You must also provide a location constraint to prevent the signal from being mapped (by the Xilinx mapper, not FPGA Express) to a dedicated clock pin.

You can lock the signal to a regular IOB in:

1. The FPGA Express constraints GUI

2. A UCF

3. The command line in FPGA Express

with an entry in the UCF that looks like this:

net clk1 LOC = P120; (where P120 is a regular I/O pin)

In an FPGA Express command line:

set_pad_loc <pin_site> /<chip_name>/<port_name>

If you are using Synplicity, Synplify will infer a global clock buffer for high fanout signals. This, accompanied by a LOC constraint (in the UCF) to a regular I/O, will cause the "OldMap:56" error. Please see (Xilinx Answer 4084) for more information.
AR# 8816
Date 08/26/2010
Status Archive
Type General Article
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