General Description: I am synthesizing an FPGA Express project, and I would like to prevent my pipeline registers from being combined into a shift register LUT. Does FPGA Express have a setting to disable this?
To work around this, write Verilog or VHDL components such that a register gets inferred:
process(clk) begin if clk'event and clk = '1' then q<=d; end if; end process;
always @ (posedge clk) q = d;
Instantiate this component as many times as needed. Make sure the "retain hierarchy" is selected when synthesizing. (You will get flip-flops instead of the SRL16's.)
The SRL16 component does not have any sets/resets. Creating a delay element with a synchronous or asynchronous set/reset will force FPGA Express to use flip-flops.
To implement a synchronous set/reset in FPGA Express, a special attribute has to be passed. For more information, please see (Xilinx Solution 3992).