General Description : When performing a Verilog behavioral simulation of the CORE Generator Binary Counter, the counter does not stop at the terminal value when the clock enable is de-asserted--it resets to zero before it stops counting.
Solution
The problem is that the behavioral model code does not take the clock enable into account when the terminal count is reached, so the count resets To correct this behavior, the clock enable signal, intCE, must be used to qualify the intSCLR_RESET assignment that is made on line 222 of the C_COUNTER_BINARY_V1_0.v model. Currently it reads: