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AR# 8898

Coregen 2.1i : ELAB2 Fatal Error: async_fifo_v1_0.vhd: not matching parameter, "q_out" in entity count_sub_reg

Description


Urgency: STANDARD



General Description:

When running behaviorial simulation with async_fifo_v1_0.vhd, the follow error message can be observed:



ELAB2: Fatal Error: ELAB2_0007

async_fifo_v1_0.vhd (3668): Length of actual

parameter (2) does not match the length of

formal parameter "q_out" (3)

(from component).

Solution


This error message is caused by an incorrectedly specified signal width for

port q_out in the module count_sub_reg in file async_fifo_v1_0.vhd.



The incorrectly written port range is found in the component declaration

of count_sub_reg in line 342:



(q_width downto 0)



The correct port range can be found in the entity declaration of

count_sub_reg in line 2262:



(q_width - 1 downto 0)



By modifying line 342, this error message will disappear.



This error is caused by a mistake in the model, async_fifo_v1_0.vhd. The component declaration for the port "q_out" in "count_sub_reg" in line 342 states that "q_out" has a range of (q_width downto 0).



The correct range for q_out should be (q_width - 1 downto 0), as shown in the entity declaration of "count_sub_reg" on line 2262. The error can be eliminated by directly modifying line 342 of async_fifo_v1_0.vhd.
AR# 8898
Date Created 08/31/2007
Last Updated 04/10/2012
Status Archive
Type General Article