General Description: My design, which consists of a Xilinx Reed Solomon core plus a wrapper, fails. The EDIF for the core appears to incorrectly try to RLOC two RAM16X1Ss and two FDCEs into a single CLB. This fails with pack errors due to contention over the SR/WE path. If mapped with the "-ir" switch to get around this problem, MAP still fails and issues the following message:
FATAL_ERROR:OldMap:bastecmput.c:1363:1.1.2.2 - Dest. pin already occupied in copypin().
There appears to be a similar conflict between the RAM161S's and FDCEs, as attaching XBLKNM attributes on the RAM161Ss keeps the problem from occurring.
Solution
1
To work around this problem, run MAP with the "-ir" switch; this tells MAP to ignore invalid RLOCs and to put XBLKNM attributes on the affected RAM16X1Ss:
This problem has been seen in the Reed Solomon Decoder core, and it occurs when the asynchronous "reset" input pin of the RS decoder core is not linked to the GSR pin of a Startup block (some synthesis tools will do this for you automatically).
Example VHDL RS Decoder wrapper file with reset connected to Startup block GSR pin:
-------------------------------------------------------------------------------- -- Reed-Solomon Decoder Wrapper Example -- Copyright 1999 Xilinx, Inc. All rights reserved. --------------------------------------------------------------------------------
This entity is intended to be used with synthesis tool optimization to produce the I/O pads and clock buffers:
LIBRARY ieee; USE ieee.std_logic_1164.ALL;
ENTITY rsdec_wrap IS PORT ( data_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0); sync : IN STD_LOGIC; reset : IN STD_LOGIC; clk : IN STD_LOGIC; ce : IN STD_LOGIC; data_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); blk_strt : OUT STD_LOGIC; blk_end : OUT STD_LOGIC; err_found : OUT STD_LOGIC; err_cnt : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); fail : OUT STD_LOGIC; ready : OUT STD_LOGIC); END rsdec_wrap;
ARCHITECTURE example OF rsdec_wrap IS
COMPONENT xil_rsdecoder PORT ( data_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0); sync : IN STD_LOGIC; reset : IN STD_LOGIC; clk : IN STD_LOGIC; ce : IN STD_LOGIC := '1'; data_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); blk_strt : OUT STD_LOGIC; blk_end : OUT STD_LOGIC; err_found : OUT STD_LOGIC; err_cnt : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); fail : OUT STD_LOGIC; ready : OUT STD_LOGIC ); END COMPONENT;
COMPONENT STARTUP PORT (GSR : IN STD_LOGIC); END COMPONENT;
COMPONENT BUFG PORT (I : IN STD_LOGIC; O : OUT STD_LOGIC); END COMPONENT;
-------------------------------------------------------------------------------- Notes About Simulation
-- Back-annotated VHDL Instantiation for accurate timing simulation
The Xilinx NGD2VHDL tool may be used to create a back-annotated netlist for the entire design (core + entity that instantiates the core) for accurate timing simulation.
-- Behavioral Model Instantiation for fast simulation
Uncomment the following CONFIGURATION to instantiate the behavioral model instead of the netlist. This example assumes the behavioral model has been compiled into the "work" library. Any higher level ENTITY that instantiates rsdec_wrap should then USE this CONFIGURATION to bind the instance correctly:
(Comment out this CONFIGURATION if the behavioral model is not to be used.)
--CONFIGURATION rsdec_wrap_config OF rsdec_wrap IS -- FOR example -- FOR decoder1 : xil_rsdecoder USE ENTITY work.rs_decoder(behavioral) -- GENERIC MAP (gen_start => 0, -- k => 188, -- n => 204, -- polynomial => 0, -- symbol_width => 8, -- c_has_ce => 1, -- c_has_erase => 0, -- c_has_sr => 0, -- sync_mode => 0, -- clks_per_sym => 1); -- END FOR; -- decoder1 -- END FOR; -- example --END rsdec_wrap_config;
Was this Answer Record helpful?
AR# 8946
Date
06/13/2002
Status
Archive
Type
General Article
By using this website, I accept the use of cookies.
Learn more