2. Support
  3. AR# 8963: 3.1i Timing Analyzer - The slave clock "CLKB" is not available as a port for creating offsets for LVDS

AR# 8963

3.1i Timing Analyzer - The slave clock "CLKB" is not available as a port for creating offsets for LVDS

Description

General Description:

In Timing Analyzer, when I select Analyze -> Analyze Against User Defined Paths by Defining Clock and I/O Timing, the slave clock "CLKB" of an LVDS pair is not available as a port for creating offset constraints.

Solution

This will be fixed in the next major software release (5.1i).

AR# 8963
Date 01/18/2010
Status Archive
Type General Article