AR# 8982

EXEMPLAR: How to do write HDL netlist for post synthesis simulation with UNISIM library? (VIRTEX only)

Description

Keyword: spectrum, leonardo, vhdl, verilog

Urgency: standard

General Description:
In LeonardoSpectrum 1999.1i and later, users can write VHDL/Verilog netilst for post synthesis
simulation with UNISIM library
See http://www.exemplar.com/support/pdf/virtex.pdf for more information.
Below is the summary of variable settings.
Note, this feature works for Virtex/Virtex-E/Spartan II devices only.

Solution

1

To generate a VHDL netlist for post synthesis simulation, set the following variables:
set xi_write_init_on_luts TRUE
set vhdl_write_component_package FALSE
set vhdl_write_use_packages "library IEEE,UNISIM; use
IEEE.std_logic_1164.all; use UNISIM.vcomponents.all;"

Once set then the netlist should be generated using "write" command:
write -format vhdl mydesign.vhdl

2

To generate a Verilog netlist for post synthesis simulation, set the following variable:
set xi_write_init_on_luts TRUE

Once set then the netlist should be generated using the "write" command:
write -format verilog mydesign.v
AR# 8982
Date 04/24/2007
Status Archive
Type General Article