AR# 8987

4.1i XST - "ERROR:Xst - file_name.v Line xx. Port 'xx' not declared."

Description

Keywords: Verilog, port, declared, module, list

Urgency: Standard

General Description:
An incomplete port listing:

module MOD20 (a, b, c);

input b;
output c;

generates the following error message in XST:

ERROR:Xst - file_name.v Line xx. Port 'xx' not declared.

Solution

To avoid this error, correct the port listing to:

module MOD20 (a, b, c);

input a, b;
output c;
AR# 8987
Date 08/06/2003
Status Archive
Type General Article