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  3. AR# 9004: 3.1i CPLD 9500XV Hitop - Only LVTTL bi-directional signals allowed

AR# 9004

3.1i CPLD 9500XV Hitop - Only LVTTL bi-directional signals allowed

Description

Keywords: 9500xv, output, banking, bi-directional

Urgency: Standard

General Description:
9500XV should allow bi-directional pins for I/O standards of LVTTL and 2.5V
LVCMOS. An error occurs when attempting to do bi-directional pins with
output standards of anything but LVTTL.

Solution

This is fixed in the latest 3.1i service pack available at:
http://support.xilinx.com/support/techsup/sw_updates/
AR# 9004
Date 08/21/2002
Status Archive
Type General Article