You are using a deprecated Browser. Internet Explorer is no longer supported by Xilinx.
2.1i XC9500 Family Hitop - Hi805 - Multiple sites/pin locks for a single signal not allowed.
Keywords: hitop, pin, lock, multiple
For Xilinx FPGAs, you may give the placer multiple sites to lock a single signal
NET dout_reg LOC=P1,P2;
When I try this syntax for the XC9500 family, I get:
hi805 - DOUT_REG is assigned to an invalid location (P1,P2) for this
device. This will prevent this design from fitting on the current
This feature was added to Xilinx software as of 4.1i.
Was this Answer Record helpful?