Description: I want to drive global clock networks from a non-dedicated clock pin. How do I do this in Synplify ?
Synplify automatically inserts primary global clock buffers (BUFGP) to clock signals. This causes Xilinx implementation tools to place the clocks at the global clock pin locations in FPGA.
To drive global buffer from the non-dedicated regular I/O, users should do the following: 1. Manually instantiate BUFG component for the clock resource 2. Assign xc_loc to the clock port.
The VHDL/Verilog examples below are tested in Synplify 5.3.1.
-- VHDL example --
library IEEE, virtex,synplify; use IEEE.std_logic_1164.all; use virtex.components.all; use synplify.attributes.all; entity setreset is port (CLK: in std_logic; DIN1, DIN2, DIN3: in STD_LOGIC; SET, RESET: in STD_LOGIC; DOUT1, DOUT2, DOUT3: out STD_LOGIC); attribute xc_loc of CLK: signal is "A11"; end setreset ;
architecture RTL of setreset is component BUFG port (i: in std_logic; o: out std_logic); end component;
signal CLKIN: std_logic; begin bufginst: BUFG port map(i => CLK, o => CLKIN);
set_then_reset: process (CLKIN, SET, RESET) begin if (SET = '1') then DOUT1 <= '1'; elsif (RESET = '1') then DOUT1 <= '0'; elsif ( CLKIN'event and CLKIN ='1') then DOUT1 <= DIN1; end if; end process;
reset_then_set: process (CLKIN, SET, RESET) begin if (RESET = '1') then DOUT2 <= '0'; elsif (SET = '1') then DOUT2 <= '1'; elsif ( CLKIN'event and CLKIN ='1') then DOUT2 <= DIN2; end if; end process;
set_only: process (CLKIN, SET) begin if (SET = '1') then DOUT3 <= '1'; elsif (CLKIN'event and CLKIN = '1') then DOUT3 <= DIN3; end if; end process; end RTL;
// Verilog example // Note: $SYNPLICITY is the Synplicity install directory.