General Description: FPGA Express does not place an IOB=TRUE constraint in the netlist on flip-flops that are in a 3-state condition, even though the "Use I/O Reg" option is enabled in the FPGA Express constraints editor.
This is a known issue, and it will be fixed in a future software release.
Meanwhile, you may work around the problem by using the "-pr b" option in MAP. This option instructs MAP to pack registers into the IOBs whenever possible.
- From the Design Manager, select Design -> Options -> Edit Implementation Options.
- In the "Optimize and Map" tab, set "Pack I/O Registers/Latches into IOBs to:" to be "Inputs and Outputs." This will turn on the "-pr b" switch.