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AR# 9076

2.1i, SYNPLIFY: xc_loc attribute does not work when applied to clock ports or BUFG (ERROR: OldMap:256 )


Keywords: synplicity, pin, buffer, bufg

Urgency: Standard

General Description:
When applying xc_loc to clock ports, one of the following happens:
1. Map produce an error:
ERROR: OldMap:256 - Clock buffer BUFG symbol "clk_50MHz_ibuf"(output
signal=clk_50MHz_c) cannot be converted to a BUFGLS due to location

This happens if LOC constraint is attached to BUFG (global buffer) instance.

2. The location constraints is ignored.
This happens if xc_loc constraint is not translated to LOC.
LOC is the constraint understood by Xilinx implementation tool.



Use LOC attribute instead of xc_loc.
See (Xilinx Solution 8055) for Verilog/VHDL syntax.

The following will set LOC in SDC file:
define_attribute {p:<clock_port>} LOC {D17}

- Replace <clock_port> with your port name. The "p:" denotes that the
constraint to be put on port, in case there is identical net or instance name.
To put constraint on instance, proceed with "i:". On nets, proceed with "n:".

- For Virtex/Virtex-E/Spartan II devices, this problem is scheduled to be fixed in
the Xilinx Alliance 3.1i release which is currently scheduled for May, 2000
and Synplify 6.0.


Alternatively, you can use UCF file to constraint the clock ports.
AR# 9076
Date 05/20/2002
Status Archive
Type General Article