We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Page Bookmarked

AR# 9077

3.1i Virtex MAP - ERROR: "DesignRules:368 - Netcheck: Sourceless. Net $3I2/..... has no source"


Keywords: BitGen, error, netcheck, sourceless, net, 368

Urgency: Standard

General Description:
When running a design through the tools, BitGen displays the following error:

"ERROR:DesignRules:368 - Netcheck: Sourceless. Net $3I2/..... has no source"


Upon further inspection, it is found that this signal is an address line to a Virtex block RAM;
there are no connections to this address line from anywhere in the device, but it has still
been assigned a net name. Looking in the MAP report will confirm that this signal is indeed
flagged as being sourceless.

This error occurs when all the block RAM WEA, ENA, RSTA, WEB, ENB, and RSTB
control lines are driven by constants and some address lines are driven by the
same constants. MAP ends up leaving undriven signal stubs on the address lines instead
of tying them off to GLOBAL_LOGIC1/0. These undriven signal stubs on the block RAMs
occur somewhat unpredictably, as they depend upon the order in which the block RAM
constants are processed during the packing phase.

This problem is fixed in the latest 3.1i Service Pack available at:

AR# 9077
Date 08/19/2002
Status Archive
Type General Article