AR# 9121

FPGA/Design Compiler - How do I instantiate and use a CLKDLL in FPGA/Design Compiler?

Description

Keywords: CLKDLL, Design, FPGA, Compiler, Virtex, Spartan-II

Urgency: Standard

General Description:
How do I instantiate and use a CLKDLL in FPGA/Design Compiler?

(Two very simple VHDL and Verilog examples with their associated scripts follow.)

Solution

1

VHDL:

library IEEE;
use IEEE.std_logic_1164.all;

entity clockdll_design is
port (clk_in : in std_logic;
rst : in std_logic;
d : in std_logic;
lock : out std_logic;
clock_out : out std_logic);
end clockdll_design;

architecture arch of clockdll_design is

component CLKDLL port(
CLKIN : in STD_LOGIC;
CLKFB : in STD_LOGIC;
RST : in STD_LOGIC;
CLK0 : out STD_LOGIC;
CLK90 : out STD_LOGIC;
CLK180 : out STD_LOGIC;
CLK270 : out STD_LOGIC;
CLK2X : out STD_LOGIC;
CLKDV : out STD_LOGIC;
LOCKED : out STD_LOGIC);
end component;

component BUFG port(i : in std_logic;
o : out std_logic);
end component;

component IBUFG port(i : in std_logic;
o : out std_logic);
end component;

signal clock_0 : std_logic;
signal feed_back : std_logic;
signal clk_in_dll : std_logic;

begin

u0 : CLKDLL
port map (CLKIN => clk_in_dll,
CLKFB => feed_back,
RST => rst,
CLK0 => clock_0,
LOCKED => lock);

u1 : BUFG
port map (I => clock_0,
O => feed_back);

u2 : IBUFG
port map (I => clk_in,
O => clk_in_dll);

process (feed_back) begin
if feed_back'event and feed_back = '1' then
clock_out<=d;
end if;
end process;


end architecture;



script:

edifout_design_name = clockdll
analyze -format vhdl clockdll.vhd
elaborate clockdll
current_design clockdll

/* set_port_is_pad "*" */

/* set_port_is_pad is commented out because */
/* Design Compiler will infer IBUFs on ports */

set_pad_type -exact IBUF d
set_pad_type -exact IBUF rst

/* list all of your inputs with the set_pad_type here */

set_pad_type -exact OBUF all_outputs()

insert_pads

compile -map_effort med
write -format edif -hierarchy -output clockdll + ".sedif"
exit

2

Verilog:

module clockdll (clock_out, lock, d, rst, clk_in);

output clock_out, lock;
input d, rst, clk_in;

reg clock_out;
wire lock;

wire d, rst, clk_in;

wire feed_back, clk_in_dll;

always @(posedge feed_back) begin

clock_out = d;

end


CLKDLL u0 (.CLKIN (clk_in_dll),
.CLKFB (feed_back),
.RST (rst),
.CLK0 (clock_0),
.LOCKED (lock));

BUFG u1 (.I (clock_0),
.O (feed_back));

IBUFG u2 (.I (clk_in),
.O (clk_in_dll));

endmodule


module CLKDLL (LOCKED, CLK0, RST, CLKFB, CLKIN);

output LOCKED, CLK0;
input CLKIN, CLKFB, RST;

endmodule

module BUFG (O, I);

output O;
input I;

endmodule

module IBUFG (O, I);

output O;
input I;

endmodule


Script:

edifout_design_name = clockdll
read -format Verilog clockdll.v
current_design clockdll

/* set_port_is_pad "*" */

/* set_port_is_pad is commented out because */
/* Design Compiler will infer IBUFs on ports */

set_pad_type -exact IBUF d
set_pad_type -exact IBUF rst

/* list all of your inputs with the set_pad_type here */

set_pad_type -exact OBUF all_outputs()

insert_pads

compile -map_effort med
write -format edif -hierarchy -output clockdll + ".sedif"
exit
AR# 9121
Date 10/01/2008
Status Archive
Type General Article