General Description: HDL Bencher provides a graphical interface to creating VHDL and Verilog Test Benches. The stimulus and expected response is stored in a Test Bench Waveform file (TBW). This file is used as an input to HDL Bencher when editing or modifying a Test Bench. This file must be manually added to each Foundation ISE project.
In Project Navigator select Source -> Add and select the <testbench>.tbw file. Once the file has been added to the project, double clicking on the file with automatically load HDL Bencher.