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AR# 9129

3.1i Foundation ISE: XST Synthesis Process Properties -- J/K option from FSM Flip Flop Extraction


Keywords: Project Navigator, Foundation ISE, J/K, XST

Urgency: Standard

General Description:
For FPGA designs using XST, the Synthesis -> Process Properties
-> HDL Options -> J/K option is invalid. XST only supports Virtex and
9500 CPLDs which do not support J/K Flip Flops.


Selecting the J/K option has no effect on synthesis or implementation
AR# 9129
Date 01/16/2003
Status Archive
Type General Article
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