AR# 9129: 3.1i Foundation ISE: XST Synthesis Process Properties -- J/K option from FSM Flip Flop Extraction
AR# 9129
3.1i Foundation ISE: XST Synthesis Process Properties -- J/K option from FSM Flip Flop Extraction
Description
Keywords: Project Navigator, Foundation ISE, J/K, XST
Urgency: Standard
General Description: For FPGA designs using XST, the Synthesis -> Process Properties -> HDL Options -> J/K option is invalid. XST only supports Virtex and 9500 CPLDs which do not support J/K Flip Flops.
Solution
Selecting the J/K option has no effect on synthesis or implementation results.