General Description: When generating an Asynchronous FIFO v1.0 with Viewlogic specified as the Design Entry vendor, the following message is encountered:
"ERROR: Viewlogic symbol generation failed. Check vllink.log for errors"
When you check the contents of the vllink.log file, you may see something like the following:
"Running vhdl2sym "
Translating file: .\fifo.vhd ERROR: fifo.vhd line 12: Syntax error near "end".
1 syntax error(s) found. Unrecoverable syntax error at line 13 in fifo. Translation process aborted. Please run VHDL analyzer for more detailed error message. "vllink done"
The problem is that the VHDL entity in the VHD file that CORE Generator uses to generate the symbol contains a syntax error. This VHD file is renamed with a .vhx extension after processing by the CORE Generator; if we examine the VHX file, we find that the entity description in it is missing a terminating ")" at the end of the entity port list.
Contents of the FIFO.VHX file:
entity fifo is port ( din : in std_logic_vector(29 downto 0); wr_en : in std_logic; wr_clk : in std_logic; rd_en : in std_logic; rd_clk : in std_logic; ainit : in std_logic; dout : out std_logic_vector(29 downto 0); full : out std_logic; empty : out std_logic; <--------------terminating parenthesis missing here end fifo;
To work around this:
1. Copy the VHX file to <your_module_name>.VHD. 2. Add in the missing parenthesis. 3. Open DOS box and run vhdl2sym on the <your_module_name>.VHD:
dos_prompt> vhdl2sym <your_module_name>.VHD
4. The new symbol file should be created and placed in your /sym directory.