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AR# 9218

LogiCORE Sine-Cosine Look-Up Table (Sin Cos LUT) v2.0 - Why do I get "ERROR: End of source encountered before closing all `endif directives" when compiling sincos_v2_0.v?


Keywords: sin, cos, compilation, simulation, library, 3.1 ISE

The following error may be seen when trying to compile the Verilog XilinxCoreLib models from

# ERROR: ./XilinxCoreLib/sincos_v2_0.v: End of source encountered before closing all `endif directives
# ERROR: /products/modeltech.ver5_4a/modeltech/bin/../sunos5/vlog failed.

The problem is that the first `ifdef declaration was not terminated with a
corresponding `endif:

// $Header: /devl/xcs/repo/env/Databases/ip/src/com/xilinx/ip/sincos_v2_0/simulation/Attic
/sincos_v2_0.v,v 2000/04/19 18:02:13 rslous Exp $

`ifdef C_SIN_COS_V2_0_DEF
`define C_SIN_COS_V2_0_DEF
`endif <---------------------------------------- This `endif is missing

`include "XilinxCoreLib/PIPELINE.v"

`ifdef C_SHIFT_FD_V1_0_DEF
`include "XilinxCoreLib/C_SHIFT_FD_V1_0.v"

`define SINE_ONLY 0
`define COSINE_ONLY 1
`define DIST_ROM 0
`define BLOCK_ROM 1
`define allUKs {C_OUTPUT_WIDTH{1'bx}}

module C_SIN_COS_V2_0 (theta, sine, cosine, nd, rfd, rdy, clk, ce, aclr, sclr);


Edit each of the .v files in your XilinxCoreLib directory, adding
in the missing `endif directive as indicated above, save the
changes, and recompile.

Please See (Xilinx Answer 30162) for a detailed list of LogiCORE Sine-Cosine Look-Up Table (Sin Cos LUT) Release Notes and Known Issues.
AR# 9218
Date 08/20/2008
Status Archive
Type General Article
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