AR# 9308


4.1i ECS - Case is not preserved in an HDL netlist that is written by ECS


Keywords: Project Navigator, ECS, VHDL, Verilog, VHF

Urgency: Standard

General Description:
When the HDL netlist is written by ECS, all symbol names are written out in lower-case characters. This may result in synthesis errors, as associated components cannot be found.


Case sensitivity can be enforced by performing the following steps:

1. Open the schematic that contains the symbol.
2. Select Edit -> Symbol and click on the symbol. This will open the Symbol Editor.
3. Select Edit -> Attributes -> Symbol Attributes, and click on the symbol.
4. In the Symbol Attributes dialog box, select "VeriModel" and enter the case-sensitive name; then, select "Enter".
5. Save the symbol and exit.
AR# 9308
Date 08/12/2003
Status Archive
Type General Article
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