AR# 9321


3.1i Trace/Timing Analyzer - Does not display coverage for FF-to-synchronous RAM paths


Keyword: timing, TRCE, trace, timing

General Description:

When I perform an analysis on my design that includes a TIMEGRP period constraint, the synchronous paths from flip-flops to distributed RAM are not covered.


To work around this problem, use a NET PERIOD constraint.

This issue will be resolved in a future release of the software.

AR# 9321
Date 01/18/2010
Status Archive
Type General Article
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