General Description: How do I use VHDL GENERATE statements to instantiate multiple instances of a CORE Generator module?
The following is an example of how to instantiate 4 instances of a CORE Generator module called "mymem":
------- MYLABEL : for i in 0 to 3 generate begin myinst : mymem port map ( <put listing of ports here> ); end generate;
: : : end myarch; ---------
-- In this case, the configuration should be configured as follows: --------- for myarch -- the architecture name for MYLABEL -- the generate loop label for all : mymem use entity XilinxCoreLib.<coregen_behavioral_model_name>(behavioral) generic map ( <list of core parameters mapped to their values from VHO snippet> ); end for; end for; end for; ----------
1. A generate loop must have a label (in this case, "MYLABEL"). 2. VHDL regards the generate loop as another level of hierarchy/scope.