UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 9412

12.1 Timing Closure - Suggestions for long carry logic chains

Description

I placed a timing constraint on a path, but the constraint has errors. What can I do to make this timing constraint pass?

Solution

You can use smaller counters to drive other counters, and cascade them so that the first counter is the enable for the second counter.

For additional suggestions and recommendations, see the following Answer Records:

- Suggestions for avoiding high fan-out signals, see (Xilinx Answer 9410).

- Suggestions for state machine optimization, see (Xilinx Answer 9411).

- Suggestions for I/Os 3-state enable paths, see (Xilinx Answer 9413).

- Suggestion for paths through TBUFs, see (Xilinx Answer 9414).

- Suggestions for timing through irrelevant paths such as RESET or ".SR" pin, see (Xilinx Answer 9415).

- Suggestions for using multi-cycle paths, such as a path through a ".CE" pin, see (Xilinx Answer 9416).

- Suggestions for how to avoid having too many levels of logic, see (Xilinx Answer 9417).

- Suggestions for timing constraints that miss their goals by 5% to 10%, see (Xilinx Answer 9418).

- Suggestions for timing constraints that miss their goals by 10% to 15%, see (Xilinx Answer 9419).

AR# 9412
Date Created 08/21/2007
Last Updated 12/15/2012
Status Active
Type General Article
Tools
  • ISE - 10.1
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • More
  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4
  • Less