AR# 9417: 12.1 Timing Closure - Suggestions for how to avoid having too many levels of logic
12.1 Timing Closure - Suggestions for how to avoid having too many levels of logic
I placed a timing constraint on a path, but the constraint has errors and too many levels of logic. How can I make this timing constraint pass?
This is a case where logic exceeds some percentage of the total path delay, implying that there is too much logic between timing end points; the amount of logic must be reduced in order to meet timing requirements. This number was traditionally around 50% for older architectures; it would need to be quantified for Virtex families (60%). There are exceptions to this rule for carry chain paths, in which the logic delays are much smaller and would allow for a higher number of logic levels or a lower component percentage. To reduce the levels of logic, return to the source and try the following: