Description

Solution

1. Issue State Machine Optimization Suggestions, see (Xilinx Answer 9411)
2. Use CASE statements instead of nested IF-ELSE statements.
3. Use 3-state instead of large muxes (7 or more inputs).
4. Use creative math; shift instead of multiplying by multiples of two.
5. Use decoders instead of comparators.
6. Balance logic around registers.
7. Pyramid logic with parentheses instead of serial implementation.
8. Use IF-THEN-ELSE statements only to do the following:
   • Pre-decode and register counter values.
   • Add a level of pipelining to pre-decode and register input signals.
9. Use muxes with more than 7-bit wide buses only to do the following:
   • Instead of logic, use registers that are in a 3-state condition.
   • Drive enable signals from registers; 3-states are in a 3-state condition when enable signals are "1," and drive signals when the enable is "0".
   • Use floorplan 3-states.
10. Add pipeline registers.

• For avoiding high fanout signals, see (Xilinx Answer 9410)
• For state machine optimization, see (Xilinx Answer 9411)
• For long carry logic chains, see (Xilinx Answer 9412)
• For I/Os 3-state enable paths, see (Xilinx Answer 9413)
• For paths through TBUFs, see (Xilinx Answer 9414)
• For timing through irrelevant paths such as RESET or ".SR" pin, see (Xilinx Answer 9415)
• For using multi-cycle paths, such as a path through a ".CE" pin, see (Xilinx Answer 9416)
• For timing constraints that miss their goals by 5% to 10%, see (Xilinx Answer 9418)
• For timing constraints that miss their goals by 10% to 15%, see (Xilinx Answer 9419)