If your constraint misses its timing requirement by less than 15%, and the logic delay is less than 60%, try several cost tables at effort level 5, using MPPR (Multi-Pass Place and Route).
For additional suggestions and recommendations, see the following Answer Records:
- Suggestions for avoiding high fanout signals, see (Xilinx Answer 9410).
- Suggestions for state machine optimization, see (Xilinx Answer 9411).
- Suggestions for long carry logic chains, see (Xilinx Answer 9412).
- Suggestions for I/Os 3-state enable paths, see (Xilinx Answer 9413).
- Suggestions for paths through TBUFs, see (Xilinx Answer 9414).
- Suggestions for timing through irrelevant paths such as RESET or ".SR" pin, see (Xilinx Answer 9415).
- Suggestions for using multi-cycle paths, such as a path through a ".CE" pin, see (Xilinx Answer 9416).
- Suggestions for how to avoid having too many levels of logic, see (Xilinx Answer 9417).
- Suggestions for timing constraints that miss their goals by 5% to 10%, see (Xilinx Answer 9418).
| AR# 9419 | |
|---|---|
| Date | 12/15/2012 |
| Status | Active |
| Type | General Article |
| Tools |
|