3.1i Virtex Map - Map fails to follow floorplan constraints.
Keywords: ERROR:Pack:679, 679, floorplan, floorplanner, MUXF6, Replace, All
Description: A case has been seen where a "Replace All With Placement" floorplanner operation and then re-map of the unchanged design using the resulting floorplan constraints leads to a Map failure:
ERROR:Pack:679 - Unable to obey design constraints (LOC = CLB_R6C26.S1) which require the combination of the following symbols into a single slice component: MUXF6 symbol "tb_comp/mux1" (Output Signal = tb_comp/TIME_BASE_MUX) FLOP symbol "tb_comp/TIME_BASE_s_reg" (Output Signal = tb_comp/TIME_BASE_s) LUT symbol "C3436" (Output Signal = tb_comp/C2/N9) There is a conflict for the GYMUX. The function generator C3436 is unable to be placed in the F position because the output signal doesn't match other symbols' use of the F signal. The signal tb_comp/mux1.F51 already uses F. Please correct the design constraints accordingly.
The problem was found to be due to the fact that the F5MUX is a route-thru inserted during mapping to reach an F6MUX and is not being correctly handled by map in the context of the floorplan constraints. The work around is to manually remove the floorplan constraints for both the F5MUX and the LUT that is driving it. They will be packed into the correct slice anyway.
This problem is scheduled to be fixed in the first major release following version 3.1i.