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AR# 9462

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EXEMPLAR, SYNPLIFY - How do I instantiate LVDS/LVPECL components in HDL? (VHDL/Verilog - Virtex-E/Spartan-IIE only)

Description


Urgency: Hot



General Description:

How do I instantiate LVPECL or LVDS components in HDL?

Solution


The following examples illustrate LVDS I/O instantiations and location constraints for V50ECS144.



To use LVPECL I/O standards, replace "LVDS" with "LVPECL" when instantiating the buffers. (For example, replace IBUF_LVDS with IBUF_LVPECL.)



For more information on LVPECL/LVDS, please reference (Xilinx XAPP133): Using the Virtex Select I/O Resource.



NOTES:

- This is a general example to use with any synthesis tool. If using Synplify, make sure the library "unisim" (VHDL) or "unisim.v" (Verilog) is included in the HDL code. Please see (Xilinx Solution 244) for more information.



- Currently, FPGA Express does not recognize IBUF_LVDS, IBUF_LVPECL, OBUF_LVDS, OBUF_LVPECL, IOBUF_LVDS and IOBUF_LVPECL as valid primitives. If you try to instantiate the LVDS buffers, FPGA Express will insert I/O buffers, causing errors when the design is run through the implementation tools. Please reference (Xilinx Solution 9849) if using this flow.



- Bidirectional LVPECL I/O is not currently supported. Please see (Xilinx Solution 8631) for more information.



- Please see (Xilinx Solution 1995) for a Synplify-specific attribute.



- Please see (Xilinx Solution 8074) for a Leonardo Spectrum-specific attribute.



VHDL example

This example contains LVDS input, output, and bidirectional I/O.



library IEEE;

use IEEE.std_logic_1164.all;

entity LVDSIO is

port (CLK, DATA, Tin : in STD_LOGIC;

IODATA_p, IODATA_n : inout STD_LOGIC;

Q_p, Q_n : out STD_LOGIC

);

end LVDSIO;





architecture BEHAV of LVDSIO is



component IBUF_LVDS is port (I : in STD_LOGIC;

O : out STD_LOGIC);

end component;



component OBUF_LVDS is port (I : in STD_LOGIC;

O : out STD_LOGIC);

end component;



component IOBUF_LVDS is port (I : in STD_LOGIC;

T : in STD_LOGIC;

IO : inout STD_LOGIC;

O : out STD_LOGIC);

end component;



component INV is port (I : in STD_LOGIC;

O : out STD_LOGIC);

end component;



component IBUFG_LVDS is port(I : in STD_LOGIC;

O : out STD_LOGIC);

end component;



component BUFG is port(I : in STD_LOGIC;

O : out STD_LOGIC);

end component;



signal iodata_in : std_logic;

signal iodata_n_out: std_logic;

signal iodata_out: std_logic;

signal DATA_int : std_logic;

signal Q_p_int : std_logic;

signal Q_n_int : std_logic;

signal CLK_int : std_logic;

signal CLK_ibufgout : std_logic;

signal Tin_int : std_logic;



begin

UI1: IBUF_LVDS port map ( I => DATA, O => DATA_int);

UI2: IBUF_LVDS port map (I => Tin, O => Tin_int);

UO_p: OBUF_LVDS port map ( I => Q_p_int, O => Q_p);

UO_n: OBUF_LVDS port map ( I => Q_n_int, O => Q_n);

UIO_p: IOBUF_LVDS port map ( I => iodata_out, T => Tin_int, IO => iodata_p,

O => iodata_in);

UIO_n: IOBUF_LVDS port map ( I => iodata_n_out, T => Tin_int, IO => iodata_n,

O => open);



UINV: INV port map ( I => iodata_out, O => iodata_n_out);

UIBUFG : IBUFG_LVDS port map ( I => CLK, O => CLK_ibufgout);

UBUFG : BUFG port map (I => CLK_ibufgout, O => CLK_int);



My_D_Reg: process (CLK_int, DATA_int)

begin

if (CLK_int'event and CLK_int='1') then

Q_p_int <= DATA_int;

end if;

end process; -- End My_D_Reg



iodata_out <= DATA_int and iodata_in;



Q_n_int <= not Q_p_int;



end BEHAV;



Verilog example

This example contains LVDS input, output, and bidirectional I/O.



module LVDSIOinst (CLK, DATA, Tin, IODATA_p, IODATA_n, Q_p, Q_n) ;

input CLK, DATA, Tin;

inout IODATA_p, IODATA_n;

output Q_p, Q_n;



wire iodata_in;

wire iodata_n_out;

wire iodata_out;

wire DATA_int;

reg Q_p_int;

wire Q_n_int;

wire CLK_int;

wire CLK_ibufgout;

wire Tin_int;





IBUF_LVDS UI1 ( .I(DATA), .O( DATA_int));

IBUF_LVDS UI2 (.I(Tin), .O (Tin_int));

OBUF_LVDS UO_p ( .I(Q_p_int), .O(Q_p));

OBUF_LVDS UO_n ( .I(Q_n_int), .O(Q_n));

IOBUF_LVDS UIO_p ( .I(iodata_out), .T(Tin_int), .IO(IODATA_p),

.O (iodata_in));

IOBUF_LVDS UIO_n ( .I (iodata_n_out), .T(Tin_int), .IO(IODATA_n),

.O ());



INV UINV ( .I(iodata_out), .O(iodata_n_out));

IBUFG_LVDS UIBUFG ( .I(CLK), .O(CLK_ibufgout));

BUFG UBUFG (.I(CLK_ibufgout), .O(CLK_int));



always @ (posedge CLK_int)

begin

Q_p_int <= DATA_int;

end



assign iodata_out = DATA_int && iodata_in;



assign Q_n_int = ~Q_p_int;



endmodule



UCF example targeting V50ECS144



NET CLK LOC = A6; #GCLK3

NET DATA LOC = A4; #IO_L0P_YY

NET Q_p LOC = A5; #IO_L1P_YY

NET Q_n LOC = B5; #IO_L1N_YY

NET iodata_p LOC = D8; #IO_L3P_yy

NET iodata_n LOC = C8; #IO_L3N_yy

NET Tin LOC = F13; #IO_L10P
AR# 9462
Date 11/23/2010
Status Archive
Type General Article
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