AR# 9462: EXEMPLAR, SYNPLIFY - How do I instantiate LVDS/LVPECL components in HDL? (VHDL/Verilog - Virtex-E/Spartan-IIE only)
EXEMPLAR, SYNPLIFY - How do I instantiate LVDS/LVPECL components in HDL? (VHDL/Verilog - Virtex-E/Spartan-IIE only)
How do I instantiate LVPECL or LVDS components in HDL?
The following examples illustrate LVDS I/O instantiations and location constraints for V50ECS144.
To use LVPECL I/O standards, replace "LVDS" with "LVPECL" when instantiating the buffers. (For example, replace IBUF_LVDS with IBUF_LVPECL.)
For more information on LVPECL/LVDS, please reference (Xilinx XAPP133): Using the Virtex Select I/O Resource.
- This is a general example to use with any synthesis tool. If using Synplify, make sure the library "unisim" (VHDL) or "unisim.v" (Verilog) is included in the HDL code. Please see (Xilinx Solution 244) for more information.
- Currently, FPGA Express does not recognize IBUF_LVDS, IBUF_LVPECL, OBUF_LVDS, OBUF_LVPECL, IOBUF_LVDS and IOBUF_LVPECL as valid primitives. If you try to instantiate the LVDS buffers, FPGA Express will insert I/O buffers, causing errors when the design is run through the implementation tools. Please reference (Xilinx Solution 9849) if using this flow.
- Bidirectional LVPECL I/O is not currently supported. Please see (Xilinx Solution 8631) for more information.