We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 9464

3.4 FPGA Express - A Verilog concatenation with an addition synthesized incorrect logic.


Keywords: FPGA, Express, 3.3, error, synthesis, results, Verilog, concatenate, add

Urgency: Hot

General Description:
FPGA Express has been seen to incorrectly synthesize Verilog code
that has a concatenation with an add. For example:

wire [16:4] temp1 = {{1{temp2[15]}}, temp2[15:4]} + temp3;


Use the following workaround. (Please notify Xilinx support if this workaround does not
solve your problem.)

Change the example code to the following:

wire [16:4] temp1 = {{1{temp2[15]}}, temp2[15:4]} + {1'b0,temp3};

FPGA Express is updated to version 3.4.3 in the latest 3.1i Service Pack available at:
The first service pack containing the fix is 3.1i Service Pack 4.

This problem is also fixed in the latest version of FPGA Express (3.5)
available at: http://support.xilinx.com/support/techsup/sw_updates.
AR# 9464
Date 08/30/2001
Status Archive
Type General Article