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AR# 9563

3.x FPGA Express - When Instantiating a Keeper to an IOBUF, I encounter "ERROR:NgdHelpers:346 - bidirect pad..."

Description

Keywords: IOBUF Keeper Express Error NgdHelpers 346 bidirect pad

Urgency: Standard

General Description:
When instantiating a Keeper in VHDL/Verilog that is connected to an IOBUF,
the following error occurs during implementation:

"ERROR:NgdHelpers:346 - bidirect pad net "name" has an
illegal connection."

This happens during synthesis, when FPGA Express assigns an OBUF
to the I/O pin of the IOBUF in the EDIF netlist.

Solution

1

The solution is to instantiate an IOPAD so that the OBUF is not inferred by the
Keeper component.

Verilog example:

`timescale 1ns / 1ns

module keepertest
( data_in, data_out,tristate
) ;


input data_in;
input tristate;
output data_out;
wire bi ;

OPAD My_OPAD(.PAD(bi));
KEEPER mykeeper(.O(bi));
IOBUF pc01 (.I(data_in),.IO(bi),.T(tristate),.O(data_out));

endmodule

2

VHDL example:

library IEEE;
use IEEE.std_logic_1164.all;

entity IOPORT is
port (
Tri: in STD_LOGIC;
input: in STD_LOGIC;
Output: out STD_LOGIC
);
end IOPORT;

architecture IOPORT_arch of IOPORT is

component OPAD port(PAD : out STD_LOGIC);
end component;

component IOBUF port(
O : out STD_ULOGIC;
IO : inout STD_ULOGIC;
I : in STD_ULOGIC;
T : in STD_ULOGIC);
end component;
component Keeper port(O : inout STD_ULOGIC);
end component;

signal bi: std_logic;

begin
My_OPAD: OPAD port map (PAD=>bi);

My_IOBUF: IOBUF port map (
O =>Output,
IO =>Bi,
I =>Input,
T =>Tri);
My_Keep: Keeper Port Map(O=>Bi);

end IOPORT_arch;
AR# 9563
Date Created 06/23/2000
Last Updated 08/11/2003
Status Archive
Type General Article