entity IOPORT is port ( Tri: in STD_LOGIC; input: in STD_LOGIC; Output: out STD_LOGIC ); end IOPORT;
architecture IOPORT_arch of IOPORT is
component OPAD port(PAD : out STD_LOGIC); end component;
component IOBUF port( O : out STD_ULOGIC; IO : inout STD_ULOGIC; I : in STD_ULOGIC; T : in STD_ULOGIC); end component; component Keeper port(O : inout STD_ULOGIC); end component;
signal bi: std_logic;
begin My_OPAD: OPAD port map (PAD=>bi);
My_IOBUF: IOBUF port map ( O =>Output, IO =>Bi, I =>Input, T =>Tri); My_Keep: Keeper Port Map(O=>Bi);