UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 9578

3.1i Foundation ISE: ECS Schematic with instantiated Verilog macros(CORE Generator) fails in XST

Description

Keywords: ECS, CORE Generator, verilog

Urgency: Standard

General Description:
When a Verilog design is synthesized and instantiated modules have not
been declared, the following error message is issued by XST:

ERROR : (VLG__5002). stopwatch.v Line 44. Module 'tenths' not defined

ECS schematic designs containing CORE Generator macros are not declared
by default. The module definition must be added to the project.

Solution

Rename the <core>.veo file to <core>.v and add it to the project.
AR# 9578
Date Created 06/26/2000
Last Updated 01/16/2003
Status Archive
Type General Article