General Description: A case has been seen involving an RLOC'd XORCY with a GND'd CI pin. The 3.1i mapper converts the XORCY to a buffer; then, because of the RLOC constraint, it gets treated as a LUT. If there are already two LUTs RLOC'd to the slice, this will result in a pack error with the message "There are more than two function generators."
In the following pack error, "U1/U1/BU2" was originally an XORCY:
ERROR:Pack:679 - Unable to obey design constraints (MACRONAME = U1/U1/hset, RLOC = R6C0.S1) which require the combination of the following symbols into a single slice component:
LUT symbol "U1/U1/BU0" (Output Signal = U1/U1/N46) LUT symbol "U1/U1/BU2" (Output Signal = P75BP<0>) LUT symbol "U1/U1/BU3" (Output Signal = U1/U1/N66) MUXCY symbol "U1/U1/BU4" (Output Signal = U1/U1/N82) XORCY symbol "U1/U1/BU5" (Output Signal = P75BP<1>) There are more than two function generators. Please correct the design constraints accordingly.
NOTE: This issue affects the Virtex, Virtex-E and Spartan-II device architectures.
NOTE: This problem is very similar to the one discussed in (Xilinx Answer #9973), which was fixed in SP4. This new fix deals with a different configuration that was not covered by the previous fix.
Meanwhile, a work-around is to override the problem XORCY RLOC with the following UCF attribute:
INST U1/U1/BU2 USE_RLOC=FALSE;
Ideally, the RLOC should only be overridden on the "LUT" symbols listed in the error that are not actually LUTs; however, you can also simply override all LUT symbols listed, and then rely on the packer to pull the LUTs into the correct slice.