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AR# 9623

FPGA Express - Positional binding is not allowed when linking the cell '...' to the target primitive design '...' FPGA-LINK-19


Keywords: Synopsys, FPGA Express, synthesis, synthesize, VHDL, Verilog, error, instantiate,
primitive, instance, FPGA, link, 19, FPGA-LINK-19, positional, binding, allowed, linking, cell,
target, primitive, design

Urgency: Standard

General Description:
When instantiating a Xilinx primitive in FPGA Express (VHDL or Verilog), I encounter the
following error message:

Positional binding is not allowed when linking the cell '...' to the target primitive design '...'


The "binding" to which this message refers is the way in which ports in your instance are
associated with ports in the component declaration (VHDL) or module declaration (Verilog).
"Positional binding" means that ports are associated by the order in which they appear in
the port list. In this case, FPGA Express wants named-based binding, rather than positional

Please note the following examples:

module GCLK ( O, I );
output O;
input I;

positional binding (ports associated by order of appearance):
GCLK my_clk (my_output, my_input); // correct
GCLK my_clk (my_input, my_output); // incorrect

name-based binding:
GCLK my_clk ( .O(my_output), .I(my_input) ); or..
GCLK my_clk ( .I(my_input), .O(my_output) );

component GCLK
port ( O : out STD_ULOGIC;
I : in STD_ULOGIC );
end component;

positional binding:
my_clk: GCLK port map ( my_output, my_input ); // correct
my_clk: GCLK port map ( my_input, my_output ); // incorrect

name-based binding:
my_clk: GCLK port map ( O => my_output, I => my_input ); or..
my_clk: GCLK port map ( I => my_input, O => my_output );

Note that you are not required to supply module declarations for primitives in Verilog.
However, you DO need to supply component declarations for primitives in VHDL.
AR# 9623
Date 08/11/2003
Status Archive
Type General Article