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  1. Xilinx - All Programmable
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  3. AR# 9641: 3.1i SP1 - 3.1i Service Pack 1 update

AR# 9641

3.1i SP1 - 3.1i Service Pack 1 update

Description

Keywords: Service, Pack, 3.1i, update,

Urgency: Standard

General Description:

Contained within this Answer is complete list of all changes included in the M3.1i Service Pack 1 Update.

Solution

The Service Pack Update Page is located at:
http://support.xilinx.com/support/techsup/sw_updates/

The following issues are addressed by the 3.1i Service Pack 1 Update:

INSTALL

(Xilinx Answer #9672) : 3.1i Service Pack Install - Canceling the
Service Pack Install gives message - Install Completed Successfully

NGDBUILD

(Xilinx Answer #9573) : 3.1i NGDBuild - Fatal-Error:Utilities:utilblist.c:234:1.4
MAX ELEMENT COUNT EXCEEDED.

MAP

(Xilinx Answer #9591) : 3.1i Virtex Map - Core dump (bus error)
during modular design assembly phase.

(Xilinx Answer #9344) : 3.1i Virtex Map - Some eligible registers
are not being packed into IOBs.

(Xilinx Answer #9077) : 3.1i Virtex Map - ERROR:DesignRules:368 -
Netcheck: Sourceless. Net $3I2/..... has no source.

PAR

(Xilinx Answer #9589) : 3.1i Virtex PAR - Guided PAR fails with
ERROR:Portability:3 - This Xilinx application has run out of memory.

(Xilinx Answer #9588) : 3.1i Virtex PAR - Range constraint expansion
in Modular Design uses too much memory.

(Xilinx Answer #9359) : 3.1i Virtex PAR- Illegal pin swaps may occur
on address pins of SRL16E.

(Xilinx Answer #9587) : 3.1i XC4000XLA PAR - Pad report does report
not all the Vcc pins for XC044XLA-HQ304.

(Xilinx Answer #9345) : 3.1i Virtex PAR - Placer crashes on designs
with RPM macros containing Block RAM.

(Xilinx Answer #9250) : 3.1i Virtex-E PAR - PAR runs out of memory
on a design with offset in constraints.

(Xilinx Answer #8937) : 3.1i Virtex PAR - PAR hangs during PWR/GND
routing.

TIMING

(Xilinx Answer #3513) : 3.1i Timing Analyzer - GDI resources taken
up when scrolling on a report.

HARDWARE DEBUGGER

(Xilinx Answer #9630) : 3.1i Hardware Debugger - Internal DCE
Threads problem while running on HP platform.

BITGEN

(Xilinx Answer #9429) : 3.1i Virtex-E BitGen - Greater than a 0.3 ns
difference seen between the input clock of a DLL and the feedback
path.

DESIGN MANAGER

(Xilinx Answer #9606) : 3.1i Design Manager - Post Layout Timing
Report should not be automatically generated after executing MPPR.

JTAG PROGRAMMER

(Xilinx Answer #9647) : 3.1i JTAG Programmer - Dr. Watson error
while trying to generate svf program device.

(Xilinx Answer #9645) : 3.1i XC1800 JTAG Programmer - XC1804 remains
in ISP mode after operation has finished.

(Xilinx Answer #9644) : 3.1i XC9500 JTAG Programmer - On programming
failure, Xilinx software does not erase the CPLD.

(Xilinx Answer #8224) : 3.1i XC18V00 JTAG Programmer - JTAG
Programmer 3.1i does not support XC18V00 SVF generation.

CPLD

(Xilinx Answer #9004) : 3.1i CPLD 9500XV Hitop - Only LVTTL
bi-directional signals allowed.

(Xilinx Answer #4100) : 3.1i XC9500 Family Hitop - PROHIBIT property
does not exclude pins from "Programmable Ground Pins" option.

(Xilinx Answer #9658) : 3.1i CPLD TAEngine - Fails to expand
wildcards [*] when processing timing constraints.

FLOORPLANNER

(Xilinx Answer #2740) : 3.1i Floorplanner - Pin constraints in ucf
file show up incorrectly in the floorplanner.

(Xilinx Answer #9033) : 3.1i Floorplanner - Error Portability 3:
application has run out of memory or Segmentation Fault.

CABLES

(Xilinx Answer #8777) : 3.1i Multilinx Cable - Issues with Win98 SE,
Win2000 and USB.

FPGA EDITOR

(Xilinx Answer #9357) : 3.1i Virtex FPGA Editor - Adding a pin to
GLOBAL_LOGIC signal leads to crash.

(Xilinx Answer #8697) : 3.1i FPGA Editor - Trace Summary selects the
wrong constraint.

COREGEN

(Xilinx Answer #9636) : 3.1i COREGEN - Foundation ISE Symbol file
not generated for Single/Dual port Block Ram cores with coefficient files.

(Xilinx Answer #9621) : 3.1i COREGEN - Foundation ISE Symbol file
not generated for FFT.

(Xilinx Answer #9098) : 3.1i COREGEN - Presence of HU_SET attributes
may cause RLOC'ing of CORE Generator modules to fail.

PACKAGE FILES

(Xilinx Answer #3149) : 3.1i Package Files - Spartan XCS10 TQ144
does not have TMS pin bonded.
AR# 9641
Date 08/19/2002
Status Archive
Type General Article