You are using a deprecated Browser. Internet Explorer is no longer supported by Xilinx.
Solutions
Products
Support
Solutions
Products
Support
Solutions by Industry
Aerospace & Defense
Back
Aerospace & Defense
Overview
Avionics & UAV
Digital RADAR/EW
MilCom & SatCom
Space
Automotive
Back
Automotive
Overview
ADAS
Automated Driving
Electrification & Networking
In-Vehicle
Broadcast & Pro A/V
Back
Broadcast & Pro A/V
Overview
AV over IP
Cameras
Converters & KVM
Encoders & Decoders
Professional Audio Systems
Professional Displays & Signage
Projection Systems
Routers & Switchers
Servers & Storage
Transmitters & Modulators
Video Conferencing
Video Processing Card
Consumer Electronics
Back
Consumer Electronics
Overview
Multifunction Printers
Ultra High Definition Televisions
Data Center
Back
Data Center
Overview
Computational Storage
Database & Data Analytics
Financial Technology
High Performance Computing
Network Acceleration
Video & Image Processing
Emulation & Prototyping
Back
Emulation & Prototyping
Overview
ASIC Emulation in Action
FPGA-Based Prototyping
Industrial
Back
Industrial
Overview
3D Printers & Additive Manufacturing
Human Machine Interface
I/O Modules & Smart Sensors
IIoT Gateways & Edge Appliances
Industrial Control with IIoT Edge Nodes
Machine & Computer Vision
Drives & Motor Control
Robotics
Smart Grid
Trains & Railways
Video Surveillance
Healthcare / Medical
Back
Healthcare / Medical
Overview
Clinical Defibrillators & Automated External Defibrillators
Diagnostic & Clinical Endoscopy Processing
Healthcare AI
Medical Imaging with CT, MRI & PET
Medical Imaging with Ultrasound
Multi-parameter Patient Monitors & ECGs
Other Medical Equipment
Robot-assisted Surgery
Safety, Security & Partner Solutions
Test & Measurement
Back
Test & Measurement
Overview
Semiconductor Automated Test Equipment
Test & Measurement Instrumentation
Wired & Wireless Testers
Wired & Wireless Communications
Back
Wired & Wireless Communications
Overview
Network Security
Telco Acceleration
Telecommunications
Wireless
Solutions by Technology
AI Inference Acceleration
Back
AI Inference Acceleration
Why Xilinx AI
Xilinx AI Solutions
Get Started with Xilinx AI
Accelerated Applications
Back
Accelerated Applications
Xilinx App Store
Reference Apps
Solutions
Products
Support
Product Categories
Devices
Back
Devices
Explore Silicon Devices
ACAPs
FPGAs & 3D ICs
SoCs, MPSoCs, & RFSoCs
Cost-Optimized Portfolio
Evaluation Boards & Kits
Back
Evaluation Boards & Kits
Explore Boards & Kits
Evaluation Boards
System-on-Modules (SoMs)
FPGA Mezzanine Cards
Board and Kit Accessories
Accelerators
Back
Accelerators
Data Center Accelerator Cards
Computational Storage
SmartNIC Accelerator
Telco Accelerator
Ethernet Adapters
Back
Ethernet Adapters
8000 Series Ethernet Adapters
X2 Series Ethernet Adapters
Software Development
Back
Software Development Tools
Vitis™ Software Platform
Vitis™ AI
Vitis™ Accelerated Libraries
Legacy Tools
Software Development Resources
Developer Site - developer.xilinx.com
Xilinx Accelerator Program
Xilinx Community Portal
Hardware Development
Back
Hardware Development Tools
Vivado® Design Suite
Intellectual Property
System Generator
Add-On for MATLAB & Simulink
Hardware Development Resources
Silicon Evaluation Boards
Design Hubs
Design and Debug Blog
Embedded Development
Back
Embedded Development
Embedded Software & Ecosystem
Xilinx Wiki Design Examples
Xilinx GitHub
Xilinx Community Portal
Core Technologies
Back
Core Technologies
Explore All Core Technologies
3D ICs
Configuration Solutions
Connectivity
Design Security
DSP
Dynamic Function eXchange
Ethernet
Functional Safety
High Speed Serial
Machine Learning
Memory
MIPI Connectivity for Imaging
PCI Express
Power Efficiency
Processing Solutions
RF Sampling
Signal Integrity
System Monitor and XADC
Accelerated Applications
Back
Accelerated Applications
Xilinx App Store
Reference Apps
Quality & Reliability
Xilinx Quality
Powered By Xilinx
Solutions
Products
Support
Support & Services
Support
Back
Support
Support Home
Knowledge Base
Documentation
Community Forums
Service Portal
Design Hubs
Versal ACAP Design Process Documentation
Downloads & Licensing
Services
Back
Services
Training
Downloads & Licensing
Product Return
University Program
Partner Design Services
Careers
Company
Back
Company
Company Overview
Management Team
Investor Relations
Xilinx Ventures
Community Engagement
Corporate Responsibility
Corporate Briefing Center
Careers
Partners
Back
Partners
Xilinx Partner Program Overview
Accelerator Partner Program
Alveo Accelerator Card Partner Network
Design Service Partners
All Ecosystem Partners
Contact Us
Back
Contact Us
Contact Xilinx
Contact Sales
Corporate Locations
Authorized Distributors
Newsroom & Media
Newsroom
Press Releases
Media Kits
Webinars
Video Portal
Powered By Xilinx
Community
Xilinx Blogs
Events
Community Forums
Shopping Cart
Sub Total
Shipping
Calculated at Checkout
Tax
Calculated at Checkout
Secure Checkout
Your cart is empty
Looks like you have no items in your shopping cart.
Click here
to continue shopping
Account
Login | Register
Sign Out
Shopping Cart
Search
All
Silicon Devices
Boards and Kits
Intellectual Property
Support
Documentation
Knowledge Base
Community Forums
Partners
Videos
Press
Search
Support
AR# 9641: 3.1i SP1 - 3.1i Service Pack 1 update
AR# 9641
Update me on changes via Email
|
Unsubscribe
3.1i SP1 - 3.1i Service Pack 1 update
Description
Solution
Description
Keywords: Service, Pack, 3.1i, update,
Urgency: Standard
General Description:
Contained within this Answer is complete list of all changes included in the M3.1i Service Pack 1 Update.
Solution
The Service Pack Update Page is located at:
http://support.xilinx.com/support/techsup/sw_updates
/
The following issues are addressed by the 3.1i Service Pack 1 Update:
INSTALL
(Xilinx Answer #9672)
: 3.1i Service Pack Install - Canceling the
Service Pack Install gives message - Install Completed Successfully
NGDBUILD
(Xilinx Answer #9573)
: 3.1i NGDBuild - Fatal-Error:Utilities:utilblist.c:234:1.4
MAX ELEMENT COUNT EXCEEDED.
MAP
(Xilinx Answer #9591)
: 3.1i Virtex Map - Core dump (bus error)
during modular design assembly phase.
(Xilinx Answer #9344)
: 3.1i Virtex Map - Some eligible registers
are not being packed into IOBs.
(Xilinx Answer #9077)
: 3.1i Virtex Map - ERROR:DesignRules:368 -
Netcheck: Sourceless. Net $3I2/..... has no source.
PAR
(Xilinx Answer #9589)
: 3.1i Virtex PAR - Guided PAR fails with
ERROR:Portability:3 - This Xilinx application has run out of memory.
(Xilinx Answer #9588)
: 3.1i Virtex PAR - Range constraint expansion
in Modular Design uses too much memory.
(Xilinx Answer #9359)
: 3.1i Virtex PAR- Illegal pin swaps may occur
on address pins of SRL16E.
(Xilinx Answer #9587)
: 3.1i XC4000XLA PAR - Pad report does report
not all the Vcc pins for XC044XLA-HQ304.
(Xilinx Answer #9345)
: 3.1i Virtex PAR - Placer crashes on designs
with RPM macros containing Block RAM.
(Xilinx Answer #9250)
: 3.1i Virtex-E PAR - PAR runs out of memory
on a design with offset in constraints.
(Xilinx Answer #8937)
: 3.1i Virtex PAR - PAR hangs during PWR/GND
routing.
TIMING
(Xilinx Answer #3513)
: 3.1i Timing Analyzer - GDI resources taken
up when scrolling on a report.
HARDWARE DEBUGGER
(Xilinx Answer #9630)
: 3.1i Hardware Debugger - Internal DCE
Threads problem while running on HP platform.
BITGEN
(Xilinx Answer #9429)
: 3.1i Virtex-E BitGen - Greater than a 0.3 ns
difference seen between the input clock of a DLL and the feedback
path.
DESIGN MANAGER
(Xilinx Answer #9606)
: 3.1i Design Manager - Post Layout Timing
Report should not be automatically generated after executing MPPR.
JTAG PROGRAMMER
(Xilinx Answer #9647)
: 3.1i JTAG Programmer - Dr. Watson error
while trying to generate svf program device.
(Xilinx Answer #9645)
: 3.1i XC1800 JTAG Programmer - XC1804 remains
in ISP mode after operation has finished.
(Xilinx Answer #9644)
: 3.1i XC9500 JTAG Programmer - On programming
failure, Xilinx software does not erase the CPLD.
(Xilinx Answer #8224)
: 3.1i XC18V00 JTAG Programmer - JTAG
Programmer 3.1i does not support XC18V00 SVF generation.
CPLD
(Xilinx Answer #9004)
: 3.1i CPLD 9500XV Hitop - Only LVTTL
bi-directional signals allowed.
(Xilinx Answer #4100)
: 3.1i XC9500 Family Hitop - PROHIBIT property
does not exclude pins from "Programmable Ground Pins" option.
(Xilinx Answer #9658)
: 3.1i CPLD TAEngine - Fails to expand
wildcards [*] when processing timing constraints.
FLOORPLANNER
(Xilinx Answer #2740)
: 3.1i Floorplanner - Pin constraints in ucf
file show up incorrectly in the floorplanner.
(Xilinx Answer #9033)
: 3.1i Floorplanner - Error Portability 3:
application has run out of memory or Segmentation Fault.
CABLES
(Xilinx Answer #8777)
: 3.1i Multilinx Cable - Issues with Win98 SE,
Win2000 and USB.
FPGA EDITOR
(Xilinx Answer #9357)
: 3.1i Virtex FPGA Editor - Adding a pin to
GLOBAL_LOGIC signal leads to crash.
(Xilinx Answer #8697)
: 3.1i FPGA Editor - Trace Summary selects the
wrong constraint.
COREGEN
(Xilinx Answer #9636)
: 3.1i COREGEN - Foundation ISE Symbol file
not generated for Single/Dual port Block Ram cores with coefficient files.
(Xilinx Answer #9621)
: 3.1i COREGEN - Foundation ISE Symbol file
not generated for FFT.
(Xilinx Answer #9098)
: 3.1i COREGEN - Presence of HU_SET attributes
may cause RLOC'ing of CORE Generator modules to fail.
PACKAGE FILES
(Xilinx Answer #3149)
: 3.1i Package Files - Spartan XCS10 TQ144
does not have TMS pin bonded.
Was this Answer Record helpful?
Yes
No
AR# 9641
Date
08/19/2002
Status
Archive
Type
General Article
People Also Viewed
Feedback
Close