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3.x FPGA Express - FPGA Express is not properly inferring BUFGs
Keywords: BUFG, BUFGLS, Spartan, XL, Spartan-XL, FPGA Express, infer
When my design includes more than 4 clock signals targeting a Spartan-XL device, FPGA Express only infers 4 BUFGs to drive the remaining clock ports by IBUFs.
If I instantiate at least one BUFG, FPGA Express does not infer BUFGs on the remaining clock ports.
When you instantiate your BUFGs, you must instantiate all that you will require. FPGA Express will stop inferring BUFGs (XC4000 architectures only) once you begin instantiating them.
You must then select the Design Manager "Translate" option "Create Pads from I/O Ports". Please see (Xilinx Answer 9691) for further information.
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