General Description: When running through PAR, the following warning might be seen:
WARNING:Place:1795 - The placement of the source component TXD11 must be in the same CLB column as the asynchronus output LVDS IOB pair $3I2/$1N104 and $3I2/$1N169. This will minimize the skew issues involving the top and bottom edges
Does this indicate a problem? If so, when can this warning be safely ignored?
This warning states that the driving CLB is not in the same column as the output pad. While this can add extra delay to that route, it will not cause an error - as long as your design can still meet timing. The warning is simply stating that there is a potentially better placement for this signal.