AR# 9671: 4.1i Virtex PAR - ERROR:Place:1613 - Design object (tmp0[15]) could not be placed
AR# 9671
4.1i Virtex PAR - ERROR:Place:1613 - Design object (tmp0[15]) could not be placed
Description
Keywords: CLB, range, SRL, SRL16, RAM, constraint
Urgency: Standard
General Description: A case has been seen where PAR reports the following errors while trying to place SRL16 components that were constrained to a CLB range in one row:
ERROR:Place:1613 - Design object (tmp0[15]) could not be placed ERROR:Place:1613 - Design object (tmp1[15]) could not be placed. ERROR:Place:1613 - Design object (tmp2[15]) could not be placed. ERROR:Place:1613 - Design object (tmp3[15]) could not be placed.
The tmp*[15] were SRL16 elements constrained to a range of CLBs in one row as follows: INST "rgn1.proc_tmp0.tmp0[15]" LOC=CLB_R6C3:CLB_R6C4 ; ... INST "rgn1.proc_tmp3.tmp3[15]" LOC=CLB_R6C3:CLB_R6C4 ;
The error in PAR occurs because the placer created a RAM macro with common address lines to minimize skew. However, the macro has a configuration that is not placable in one row.
Solution
This problem will be fixed in the next major release following 4.1i.
Meanwhile, a work-around is to set the following environment variable, which disables the placer macro creation.: