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AR# 9682

3.1i SIMPRIMS - X_CLKDLL2 model simulates the CLKDV port inconsistently. (VHDL)

Description

Keywords: SIMPRIMS, X_CLKDLL2, simulation, back-annotated, timing,
error, incorrect

Urgency: Standard

General Description:
In some Virtex-E and Virtex-II designs, the CLKDV signal is
synched to the falling edge of CLKIN. Is this an error?

Solution

Yes, this is an error. The CLKDV signal should be in sync with the
rising edge of CLK0/CLKIN.

This problem is fixed in the latest 3.1i Service Pack available at:
http://support.xilinx.com/support/techsup/sw_updates. The first
service pack containing the fix is 3.1i Service Pack 4.
AR# 9682
Date Created 08/31/2007
Last Updated 09/05/2002
Status Archive
Type ??????