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  3. AR# 9685: LogiCORE Reed Solomon - Can the Xilinx RS Cores implement specifications of ISS 308?

AR# 9685

LogiCORE Reed Solomon - Can the Xilinx RS Cores implement specifications of ISS 308?

Description

Keywords: Core, Reed, Solomon, ISS, 308, 309, DSP

Can the Xilinx RS Cores implement specifications of ISS 308?
If so, what are the Core sizes?

Solution

The RS cores do support the IESS-308 standard.
The IESS-308 standard actually specifies 5 different
RS codes. The parameters for 4 of these can be seen
by going to the demo GUI at:

http://www.xilinx.com/products/logicore/reed_sol/rsdec/cgen_demo/xrsdecClientA100.html

and selecting the IESS code specification
from the drop-down list.

We have tried generating cores with these parameters
and get the following results for decoders/encoders:


Decoder (no erasures) Decoder (with erasures) Encoder
(225,205) - 810 slices + 3 block RAMs, 1777 slices + 3 block RAMs, 120 slices
(219,201) - 742 slices + 2 block RAMs, 1627 slices + 3 block RAMs, 111 slices
(208,192) - 666 slices + 2 block RAMs, 1467 slices + 3 block RAMs, 97 slices
(194,178) - 672 slices + 2 block RAMs, 1469 slices + 3 block RAMs, 97 slices
(126,112) - 627 slices + 2 block RAMs, 1300 slices + 2 block RAMs, 94 slices


Note that if continuous code blocks are required then 2 or more
clock cycles per symbol will have to be used, except for
the (126,112) code. This example just used 1 clock cycle per symbol
but it makes little difference to the overall size.


Please See (Xilinx Answer 30176) for a detailed list of LogiCORE Reed Solomon Decoder Release Notes and Known Issues.
Please See (Xilinx Answer 30177) for a detailed list of LogiCORE Reed Solomon Encoder Release Notes and Known Issues.
AR# 9685
Date 03/13/2008
Status Archive
Type General Article

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