AR# 970: Defining pin attributes/locations for a VHDL code using Viewsynthesis
AR# 970
Defining pin attributes/locations for a VHDL code using Viewsynthesis
Description
This describes how some attributes can be added to the IO pins using Viewsynthesis.
Solution
A DESIGN.FPN file needs to be created in the project directory with the following commands:
| a comment | Define location TOP-RIGHT for pin RST bufatt RST loc=tr | Define location p13 and FAST output for pin outt[7] bufatt outt[7] loc=p13, fast
Note that the line: bufatt RST loc=tr causes the RST pad to be located "tr" (or "top right").
Note that the line: bufatt outt[7] loc=p13,fast ends up as attributes on the outt[7] pad -- it is to be located at pad p13, and to be a "fast" slew-rate pad.
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AR# 970
Date
11/08/2004
Status
Archive
Type
General Article
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