UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
  1. Xilinx - All Programmable
  2. Support
  3. AR# 9728: CPLD - Can signals be applied to CPLD I/Os before power is supplied?

AR# 9728

CPLD - Can signals be applied to CPLD I/Os before power is supplied?

Description

Can a signal be applied to a CPLD I/O pin before VCC or VCCIO is supplied to the device?

Solution

Yes it can. The voltage permitted varies with the device. Consult the appropriate data sheet and look for the Vin maximum specification.

AR# 9728
Date 12/15/2012
Status Active
Type General Article
Page Bookmarked