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  3. AR# 9755: VSS - How do I compile Xilinx Simulation Libraries for VSS?

AR# 9755

VSS - How do I compile Xilinx Simulation Libraries for VSS?

Description

Keywords: Synopsys, VSS, VHDLAN, VHDLSIM, simulation, how

Urgency: Standard

General Description:
How do I compile Xilinx simulation libraries in Synopsys VSS?

Solution

1

Manually compiling the libraries:

VSS is Synopsys' VHDL simulator, and it uses pre-compiled libraries for simulation. Xilinx provides compiled simulation libraries for VSS, which can be found at: $XILINX/synopsys/libraries/sim/.

VSS uses the .synopsys_vss.setup file for environment and library settings. An example of this file is provided in the $XILINX/synopsys/examples directory. Pointers to the simulation libraries must be modified to reflect their actual location.

The following procedure illustrates how to compile the Xilinx simulation libraries:

LogiBLOX: The LogiBLOX library is used for designs containing LogiBLOX components during pre-synthesis (RTL) and post-synthesis simulation.

- Add the following line to the .synopsys_vss.setup file:
LOGIBLOX : /path_to_directory/logiblox

- Create the physical directory as follows:
mkdir /path_to_directory/logiblox

- Then, compile the library in VSS:
vhdlan -c -w LOGIBLOX $XILINX/vhdl/src/logiblox/mvlutil.vhd
vhdlan -c -w LOGIBLOX $XILINX/vhdl/src/logiblox/mvlarith.vhd
vhdlan -c -w LOGIBLOX $XILINX/vhdl/src/logiblox/logiblox.vhd

SimPrim: The SimPrim library is used for post-NGDBuild (gate-level functional), post-MAP (partial timing), and post-place-and-route (full timing) simulations.

- Add the following line to the .synopsys_vss.setup file:
SIMPRIM: /path_to_directory/simprims

- Create the physical directory as follows:
mkdir /path_to_directory/simprims

- Then, compile the library in VSS:
vhdlan -c -w SIMPRIM $XILINX/vhdl/src/simprims/simprim_Vpackage.vhd
vhdlan -c -w SIMPRIM $XILINX/vhdl/src/simprims/simprim_Vcomponents.vhd
vhdlan -c -w SIMPRIM $XILINX/vhdl/src/simprims/simprim_VITAL.vhd

UniSim: The UniSim library is used for behavioral (RTL) simulation with instantiated components in the netlist and for post-synthesis simulation.

- Add the following line to the .synopsys_vss.setup file:
UNISIM : /path_to_directory/unisims

- Create the physical directory as follows:
mkdir /path_to_directory/unisims

- Then, compile the library in VSS:
vhdlan -c -w UNISIM $XILINX/vhdl/src/unisims/unisim_VPKG.vhd
vhdlan -c -w UNISIM $XILINX/vhdl/src/unisims/unisim_VCOMP.vhd
vhdlan -c -w UNISIM $XILINX/vhdl/src/unisims/unisim_VITAL.vhd

CORE Generator: The CORE Generator HDL library models are used for RTL simulation.

- Add the following line to the .synopsys_vss.setup file:
XILINXCORELIB : /path_to_directory/xilinxcorelib

- Create the physical directory as follows:
mkdir /path_to_directory/xilinxcorelib

- Then, compile the library in VSS:
vhdlan -i -w xilinxcorelib /path_to_directory/<filename>.vhd

NOTE: A specific order of compilation needs to be followed for CORE Generator VHDL models. This order can be found in the file "$XILINX/vhdl/src/XilinxCoreLib/vhdl_analyze_order".

2

For information on simulating designs using VSS, please see (Xilinx Answer 9774).

3

For the Xilinx 4.1i/4.2i software:

Xilinx provides a utility that compiles the HDL libraries for the VSS simulator. This utility is available at $XILINX/bin/<platform>/compile_hdl.pl
(where <platform> is hp, sol, or nt).

To run this, type the following at the command-line:

xilperl compile_hdl.pl
AR# 9755
Date 09/27/2008
Status Archive
Type General Article