AR# 9780

FPGA Express 3.x - Net preservation of internal nets using the KEEP attribute

Solution

The only way to keep a net in FPGA Express is to instantiate a BUF primitive in the middle of the net, place a "dont_touch" attribute on the BUF (through FPGA Express' Constraints Editor), then place a KEEP implementation constraint on the net that enters the BUF and on the net that exits the BUF.

Placing the dont_touch attribute (using ISE):

1. Expand the "Synthesize" process in the "Process View" window.

2. Expand "Create Functional Structure" within the "Synthesize" process.

3. Double-click on "Edit Constraints".

4. Select the "Modules" tab from within Constraints Editor.

5. Under the "Dont Touch" column, select "True" for the instantiated BUF.

6. Select the "OK" button.

NOTE: If using FPGA Express standalone deselect the 'Skip Constraint Entry' box located at the bottom of the 'Create Implementation Window'. Then follow steps 4 - 6.

Placing the KEEP implementation constraint (within ISE):

1. From Project Navigator, select File -> Open (Ctrl+O).

2. Find the project_name.ucf file.

3. Enter the two constraints:

NET buf_input_net_name KEEP;

NET buf_output_net_name KEEP;

VHDL code for instantiating a BUF primitive:

library ieee;

use ieee.std_logic_1164.all;

entity ff is

port (a : in std_logic;

b : in std_logic;

clk : in std_logic;

q : out std_logic);

end entity;

architecture ff_arch of ff is

signal d, d_int : std_logic;

component BUF is

port (I : in std_logic;

O : out std_logic);

end component;

begin

process (clk) is

begin

d <= a AND b;

if clk'event and clk = '1' then

q <= d_int;

end if;

end process;

u0 : BUF port map (d, d_int);

end architecture;

Verilog code for instantiating a BUF primitive:

module ff (a, b, clk, q);

input a, b, clk;

output q;

wire d, d_int;

reg q;

assign d = a & b;

always @(posedge clk) q <= d_int;

BUF u0 (.I(d), .O(d_int));

endmodule

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AR# 9780
Date	08/02/2010
Status	Archive
Type	General Article

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