We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 9814

3.1i XST - ERROR: (VLG__5002). <path>\<file_name> Line ##. Continuous assignment lval '<bus_name>' not a net


Keywords: Verilog, continuous, bus, bit, bit-wise, wise

Urgency: Standard

General Description:
The Verilog construct:

assign net_name = & ~bus_name;

may produce the following error if you try to perform a bit-wise operation on a negated bus:

ERROR: (VLG__5002). <path>\<file_name> Line ##. Continuous assignment lval '<bus_name>' not a net


The above Verilog construct is legal.

To work around the problem, add parentheses around the bus name (including the negation operator).

assign net_name = & (~bus_name);

NOTE: This problem is fixed in the 4.1i software release.
AR# 9814
Date 08/20/2002
Status Archive
Type General Article