General Description: When I write HDL that should infer an FDCE for an XC9500XL device, FPGA Express infers an FDCPE. (The FDCPE is a macro comprised of the primitive FDCP, plus other logic that does not use the dedicated clock enable line included in the XC9500XL family.)
The VHDL and Verilog code that should infer an FDCE is as follows:
VHDL:
library ieee; use ieee.std_logic_1164.all;
entity test is port (data : in std_logic; clk : in std_logic; en : in std_logic; q : out std_logic); end entity;
architecture arch_test of test is begin
process (clk) begin if clk'event and clk = '1' then if en = '1' then q<=data; end if; end if; end process; end architecture;
Verilog:
module test(data,clk,en,q);
input data,clk,en; output q; reg q ;
always@(posedge clk) begin if (en) q <= data; end endmodule
Solution
If the FDCE is necessary, the only solution is to have instantiated it.
VHDL:
library ieee; use ieee.std_logic_1164.all;
entity ff is port (data: in std_logic; clk : in std_logic; en : in std_logic; q : out std_logic); end entity;
architecture ff_arch of ff is
component FDCE port (D : in std_logic; C : in std_logic; CE : in std_logic; CLR : in std_logic; Q : out std_logic); end component;