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3.1i XST - "WARNING: (FCT__0300). Model 'module_name' has different characteristics in destination library"
Keywords: Verilog, library, primitive, instantiate
If a user module/component (black box or functional) and a Xilinx primitive have the same name, the XST mapper will rename the user module/component.
"xor4" will be renamed to "xor41."
The warning messages from XST are:
WARNING: (FCT__0300). Model 'xor4' has different characteristics in destination library
WARNING: (FCT__0301). Model name has been changed to 'xor41'
Although Verilog is case-sensitive, this occurs for both VHDL and Verilog Synthesis, regardless of case.
To avoid these warnings, change the name of the user made module/component to something that is a non-primitive name. The list of primitives that XST recognizes can be found in:
NOTE: This issue is fixed in the 4.1i software release.
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