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  3. AR# 9887: 7.1i XST - "ERROR:Xst:917 - Undeclared signal <signal_name>"

AR# 9887

7.1i XST - "ERROR:Xst:917 - Undeclared signal <signal_name>"

Description

Keywords: array, bus, wide

Urgency: Standard

General Description:
XST erroneously issues the error message:

"ERROR:Xst:917 - Undeclared signal <signal_name>."

Below are several identified problems.

Solution

1

XST will also report this error if a reg data type is declared within an "always" procedural block, as in the following:

module TEST(input clk, input rst);
:
:
always @ (clk or rst)
begin: COMPUTE_PROC
reg [0:0] CLAV [2:0];
CLAV[0] = 1'bx;
CLAV[1] = 1'bx;
CLAV[2] = 1'bx;
end
:
:
endmodule

XST will accept the code if the signal CLAV is declared outside of the "always" block:

module TEST(input clk, input rst);
:
:
reg [0:0] CLAV [2:0];

always @ (clk or rst)
begin: COMPUTE_PROC
CLAV[0] = 1'bx;
CLAV[1] = 1'bx;
CLAV[2] = 1'bx;
end
:
:
endmodule

2

When a bus-wide array declaration is performed in a Verilog function:
reg [32:1] signal_name [8:0];

XST will generate the following error message:
"ERROR:Xst:917 - Undeclared signal <signal_name>."

This is because XST does not support bus-wide array declarations in functions. The only solution is to break the array down into individual buses in the following manner:

reg [8:0] signal_name_1;
reg [8:0] signal_name_2;
reg [8:0] signal_name_3;
:
:
reg [8:0] signal_name_32;

NOTE: The problem of declaring a bus-wide array was resolved in the 5.1i software release.

3

XST will also report this error if you have instantiated a Verilog file that includes a state machine in a VHDL file. The Verilog state machine will have the state names declared with parameters, such as in the following example:

parameter [3:0]
S1 = 2'b01,
S2 = 2'b10;

reg [3:0] CS;
reg [3:0] NS;

always @ (posedge CLOCK or posedge RESET)
begin
if (RESET) CS <= S1;
else CS <= NS;
end

always @ (CS or /*<other inputs>*/)
begin
case (CS)
S1: begin
Q <= 0;
NS <= S2;
end
S2: begin
Q <= 1;
NS <= S1;
end
endcase
end

To work around this issue, use a `define instead of parameter to declare your state names. Be sure to use the ` symbol in every place you use a state name:

`define S1 2'b01
`define S2 2'b10

reg [3:0] CS;
reg [3:0] NS;

always @ (posedge CLOCK or posedge RESET)
begin
if (RESET) CS <= `S1;
else CS <= NS;
end

always @ (CS)
begin
case (CS)
`S1: begin
Q <= 0;
NS <= `S2;
end
`S2: begin
Q <= 1;
NS <= `S1;
end
endcase
end

4

XST will also generate the above error message when parameters are declared within functions:

function [fifo_addr_width - 1:0] bin2gray;
input [fifo_addr_width - 1:0] input_bin;

parameter DEPTH_SIZE = 4;
// bin2gray
integer input_bin_int;
integer output_gray_int;
reg [DEPTH_SIZE - 1:0] depth;
:
:


The work around is to declare the parameter outside the body of the function. This limitation will be fixed in a future version of XST.
AR# 9887
Date 07/18/2007
Status Archive
Type General Article