AR# 9910

Description

General Description:

How do I work around COREGen symbol generation failures in ECS?

Depending on the core, you may or may not get following error

during the core generation:

Errors or warnings compiling C:\coregen_test\test_ise\core_name.asy.

Warning line 17: Pin attribute not defined

Solution

Verilog

- Rename the module's VEO file to <module_name>.v

- Add the .v file to a Project Navigator Verilog project. To

specify a Verilog project, you must set the "Design Flow" for the project

to some type of Verilog design flow (either "XST Verilog," or "FPGA

Express Verilog"):

Project-> Add Source

Now look at the Process window, located below the Project window

in Project Navigator. With the new .v file selected in your Project

window, select the following in the Process window:

- Design Utilities-> Create Schematic Symbol (then double-click)

You should see a .SYM file added to the project directory.

VHDL

For cores that come with a fixed .VHD behavioral model (for example,

fixed cores like the XCA LogiCOREs), you can use the .VHD behavioral

model instead of the .VEO file as the input for the schematic symbol

generation.

(Note: .VHO files cannot be used for this purpose because they

only consist of VHDL code snippets; as a result, they will not

pass Project Navigator's syntax checking.)

- Add the .VHD file to a Project Navigator VHDL project. The "Design Flow"

for the project must be set to some type of VHDL design flow (either "XST

VHDL," or "FPGA Express VHDL"):

Project-> Add Source

Now look at the Process window, located below the Project window in

the Project Navigator. With the new .VHD selected in your Project window,

select the following in the Process window:

- Design Utilities-> Create Schematic Symbol (then double-click)

You should see a .SYM file added to the project directory.