AR# 9919: 3.1i NGDBuild- ERROR:NgdBuild:467 - output pad net 'xx' has an illegal buffer
AR# 9919
3.1i NGDBuild- ERROR:NgdBuild:467 - output pad net 'xx' has an illegal buffer
Description
Keywords: Project Navigator, ngdbuild, driver
Urgency: Standard
General Description: Several macros included in the Xilinx Unified Library contain output buffers (OBUF). When a user connects one of these macro outputs to an OBUF, the following error occurs:
ERROR:NgdBuild:467 - output pad net 'XX' has an illegal buffer
Solution
1
Remove the OBUF connected to the macro. Refer to the Xilinx Libraries Guide for a complete list of macros containing OBUFs.
2
If you are instantiating buffers in your HDL code (e.g., Select I/O buffers), ensure that the synthesis tool is not inserting redundant I/O buffers.
Foundation ISE: Right-click on "Synthesize" in the "Processes" window and select "Properties."
FPGA Express: Deselect "Insert I/O Pads."
XST: Deselect "Add I/O Buffers" under "Xililnx Specific Options."
Foundation: Open your design in stand-alone FPGA Express and select the top level design file from the list window at the top of the GUI. This will bring up a window in which you can select "Do Not Insert I/O Pads" and re-synthesize.
To open your design in stand-alone FPGA Express: 1. Open the program via Start -> Programs -> Foundation -> Accessories -> FPGA Express 2. Your project is located in C:\my_proj\my_proj\my_proj.exp
3
This error may also be caused in Foundation ISE when instantiating cores in Verilog. No Xilinx cores should contain IBUF or OBUF, but if you synthesize a core's wrapper file, the synthesis tool will optimize out the core and leave buffers on the outputs. This will cause the above error due to the doubling up of the output buffers. The solution is to regenerate the core .edn file and synthesize the top level design module rather than the core wrapper.
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AR# 9919
Date
12/07/2004
Status
Archive
Type
General Article
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